Optimizing BVH Traversal in Ray-Tracers
Exploring cache-friendly memory layouts for Bounding Volume Hierarchies and SIMD-accelerated intersection tests to minimize pipeline stalls during complex scene traversal.
Technical Log
Deep dives into systems programming, computer graphics, and architecture.
Warp Efficiency in CUDA Kernels
Understanding divergence patterns and optimizing memory access patterns for maximum occupancy in high-throughput compute kernels.